www.siliconstandard.com 1 of 7 ssm 4507m re v . 1 . 01 4 /06 /2004 complementary n and p-channel enhancement-mode power mosfets simple d rive r equirement n-c h bv dss 30v lower g ate c harge r ds(on) 36m w fast s witching p erformance i d 6.0a p-c h bv dss -30v r ds(on) 72m w description i d -4.2a absolute maximum ratings symbol parameter rating units n-channel p-channel v ds drain-source voltage 30 -30 v v gs gate-source voltage 20 20 v i d @t a =25 c continuous drain curren t 3 6 -4.2 a i d @t a =70 c continuous drain curren t 3 4.8 -3.4 a i dm pulsed drain current 1 20 -20 a p d @t a =25 c total power dissipation 2.0 w linear derating factor 0.016 w/ c t stg storage temperature range -55 to 150 c t j operating junction temperature range -55 to 150 c symbol value unit rthj-a thermal resistance junction-ambient 3 max. 62.5 c /w parameter thermal data advanced power mosfets from s ilicon sta ndard provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost- effectiveness. the so-8 package is wi de l y preferred for commercial and industrial surface mount applications and is we ll suited for low - voltage applications such as dc/dc converters. s1 g1 s2 g2 d1 d1 d2 d2 g2 d2 s2 g1 d1 s1 s1 g1 s2 g2 d1 d1 d2 d2 so-8 www..net
www.siliconstandard.com 2 of 7 ssm 4 5 07 m re v . 1 . 01 4 /06 /2004 n- c hanne l electrical characteristics @ t j =2 5 o c (unless otherwise specified) symbol parameter test conditions min. typ. max. units bv dss drain-source breakdown voltage v gs =0v, i d =250ua 30 - - v d b v dss / d t j breakdown voltage temperature coefficient reference to 25 c , i d =1ma - 0.02 - v / c r ds(on) static drain-source on-resistance 2 v gs =10v, i d =6a - - 36 m w v gs =4.5v, i d =4a - - 60 m w v gs(th) gate threshold voltage v ds =v gs , i d =250ua 1 - 3 v g fs forward transconductance v ds =10v, i d =6a - 8 - s i dss drain-source leakage current (t j =25 o c) v ds =30v, v gs =0v - - 1 ua drain-source leakage current (t j =70 o c) v ds =24v, v gs =0v - - 25 ua i gss gate-source leakage v gs =20v - - na q g total gate charge 2 i d =6a - 6 10 nc q gs gate-source charge v ds =24v - 2 - nc q gd gate-drain ("miller") charge v gs =4.5v - 3 - nc t d(on) turn-on delay time 2 v ds =15v - 7 - ns t r rise time i d =1a - 6 - ns t d(off) turn-off delay time r g =3.3 w, vgs =10v - 15 - ns t f fall time r d =15 w - 4 - ns c iss input capacitance v gs =0v - 430 690 pf c oss output capacitance v ds =25v - 100 - pf c rss reverse transfer capacitance f=1.0mhz - 70 - pf source-drain diode symbol parameter test conditions min. typ. max. units v sd forward on voltage 2 i s =6a, v gs =0v - - 1.2 v t rr reverse recovery time 2 i s =6a, v gs =0v - 19 - ns q rr reverse recovery charge di/dt=100a/s - 11 - nc 100 www..net
www.siliconstandard.com 3 of 7 ssm 4 5 07 m re v . 1 . 01 4 /06 /2004 p-channel electrical characteristics @ t j =25 o c (unless otherwise specified) symbol parameter test conditions min. typ. max. units bv dss drain-source breakdown voltage v gs =0v, i d =-250ua -30 - - v d bv dss /d t j breakdown voltage temperature coefficient reference to 25c,i d =-1ma - -0.02 -v/c r ds(on) static drain-source on-resistance 2 v gs =-10v, i d =-4a - - 72 mw v gs =-4.5v, i d =-2a - - 120 mw v gs(th) gate threshold voltage v ds =v gs , i d =-250ua -1 - -3 v g fs forward transconductance v ds =-10v, i d =-4a - 7.2 - s i dss drain-source leakage current (t j =25 o c) v ds =-30v, v gs =0v - - -1 ua drain-source leakage current (t j =70 o c) v ds =-24v, v gs =0v - - -25 ua i gss gate-source leakage v gs =20v - - na q g total gate charge 2 i d =-4a - 6 10 nc q gs gate-source charge v ds =-24v - 1 - nc q gd gate-drain ("miller") charge v gs =-4.5v - 3 - nc t d(on) turn-on delay time 2 v ds =-15v - 8 - ns t r rise time i d =-1a - 7 - ns t d(off) turn-off delay time r g =3.3w ,v gs =-10v - 18 - ns t f fall time r d =15w -4- ns c iss input capacitance v gs =0v - 400 640 pf c oss output capacitance v ds =-25v - 90 - pf c rss reverse transfer capacitance f=1.0mhz - 65 - pf source-drain diod e symbol parameter test conditions min. typ. max. units v sd forward on voltage 2 i s =-4a, v gs =0v - - -1.2 v t rr reverse recovery time 2 i s =-4a, v gs =0v - 15 - ns q rr reverse recovery charge di/dt=-100a/s - 20 - nc notes: 1.pulse width limited by max. junction temperature. 2.pulse width < 300us , duty cycle < 2%. 3.surface mounted on 1 in 2 copper pad of fr4 board ; 135c/w when mounted on min. copper pad. 100 www..net
www.siliconstandard.com 4 of 7 ssm 4 5 07 m re v . 1 . 01 4 /06 /2004 n-channel fig 1. typical output characteristics fig 2. typical output characteristics fig 3. on-resistance vs. gate voltage fig 4. normalized on-resistance vs. junction temperature fig 5. forward characteristic of fig 6. gate threshold voltage vs. reverse diode junction temperature 0 5 10 15 20 25 01122334 v ds , drain-to-source voltage (v) i d , drain current (a) t a =150 o c v g =3.0v 10v 7.0v 5.0v 4.5v 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -50 0 50 100 150 t j ,junction temperature ( o c) normalized r ds(on) i d =6a v g =10v 0.5 1 1.5 2 2.5 3 -50 0 50 100 150 t j ,junction temperature ( o c) v gs(th) (v) 0 1 2 3 4 5 6 0 0.2 0.4 0.6 0.8 1 1.2 v sd , source-to-drain voltage (v) i s (a) t j =25 o c t j =150 o c 0 5 10 15 20 25 30 35 40 012345 v ds , drain-to-source voltage (v) i d , drain current (a) t a =25 o c 10 v 7.0v 5.0v 4.5v v g =3.0v 26 31 36 41 46 51 56 61 35791 1 v gs , gate-to-source voltage (v) r ds(on) (m w ) i d =4a t a =25 o c www..net
www.siliconstandard.com 5 of 7 ssm 4 5 07 m re v . 1 . 01 4 /06 /2004 n-channel fig 7. gate charge characteristics fig 8. typical capacitance characteristics fig 9. maximum safe operating area fi g 10. effective transient thermal im p edanc e fig 11. switching time waveform fig 12. gate charge waveform t d(on) t r t d(off) t f v ds v gs 10% 90% q v g 4.5v q gs q gd q g charge 0 2 4 6 8 10 12 024681 01 2 q g , total gate charge (nc) v gs , gate to source voltage (v) i d =6a v ds =24v 10 100 1000 1 5 9 1 31 72 12 52 9 v ds , drain-to-source voltage (v) c (pf) f =1.0mhz c iss c oss c rss 0.001 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 1000 t , pulse width (s) normalized thermal response (r thja ) p dm duty factor = t/t peak t j = p dm x r thja + t a rthja=135 o c/w t t 0.02 0.01 0.05 0.1 0.2 duty factor=0.5 single pulse 0.01 0.1 1 10 100 0.1 1 10 100 v ds , drain-to-source voltage (v) i d (a) t a =25 o c single pulse 1ms 10ms 100ms 1s 10s dc www..net
www.siliconstandard.com 6 of 7 ssm 4 5 07 m re v . 1 . 01 4 /06 /2004 fig 3. on-resistance vs. gate voltage fig 4. normalized on-resistance vs. junction temperature fig 5. forward characteristic of fig 6. gate threshold voltage vs. reverse diode junction temperature 0.6 0.8 1.0 1.2 1.4 1.6 -50 0 50 100 150 t j , junction temperature ( o c) normalized r ds(on) i d =-4a v g =-10v 0 1 2 3 4 5 0 0.2 0.4 0.6 0.8 1 1.2 -v sd , source-to-drain voltage (v) -i s (a) t j =25 o c t j =150 o c 50 60 70 80 90 100 35791 1 -v gs ,gate-to-source voltage (v) r ds(on) (m w ) i d =-2a t a =25 o c 0.5 1 1.5 2 2.5 -50 0 50 100 150 t j , junction temperature ( o c) -v gs(th) (v) p-channel fig 1. typical output characteristics fig 2. typical output characteristics 0 5 10 15 20 25 30 012345 -v ds , drain-to-source voltage (v) -i d , drain current (a) t a =150 o c v g =-3.0v -10v -7.0v -5.0v -4.5v 0 10 20 30 40 012345 -v ds , drain-to-source voltage (v) -i d , drain current (a) -10 v -7.0v -5.0v -4.5v v g =-3.0v t a =25 o c www..net
in formation furnished by silicon standard corporation is believed to be accurate and reliable. however, silicon standard corporation makes no guarantee or warranty, expre ss or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. silicon standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. no license is granted, whether expressly or by im plication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of silicon standard corporation or any third parties. www.siliconstandard.com 7 of 7 ssm 4 5 07 m re v . 1 . 01 4 /06 /2004 p-channel 0 2 4 6 8 10 12 0.0 2.5 5.0 7.5 10.0 12.5 q g , total gate charge (nc) -v gs , gate to source voltage (v) i d =-4a v ds =-24v 10 100 1000 1 5 9 13 17 21 25 29 -v ds , drain-to-source voltage (v) c (pf) f =1.0mhz c iss c oss c rss fig 7. gate charge characteristics fig 8. typical capacitance characteristics fig 9. maximum safe operating area fig 10. effective transient thermal impedance 0.01 0.1 1 10 100 0.1 1 10 100 -v ds , drain-to-source voltage (v) -i d (a) t a =25 o c single pulse 1ms 10ms 100ms 1s 10s dc 0.001 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 1000 t , pulse width (s) normalized thermal response (r thja ) p dm duty factor = t/t peak t j = p dm x r thja + t a rthja=135 o c/w t t 0.02 0.01 0.05 0.1 0.2 duty factor=0.5 single pulse t d(on) t r t d(off) t f v ds v gs 10% 90% q v g -4.5v q gs q gd q g charge fig 11. switching time waveform fig 12. gate charge waveform www..net
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